AT90SCR100 datasheet(61/433 Pages) ATMEL

61 / 433 page

TPR0327AY–SMS–30Jan09

AT90SCR100

This bit is set and cleared by software. Set this bit to enable interrupt generation as soon as Vcc

drops below the Supply Monitor level. The global interrupt bit (SREG.I) should be set.

Clear this bit to mask Supply Monitor Interruption generation.

• Bit 5..1 – Reserved Bits

These bits are reserved for future use.

• Bit 0 – SMONEN: Supply Monitor Enable

This bit is set and cleared by software. Setting this bit will activate the Supply Monitor system.

Clearing this bit will disable the Supply Monitor system and reduce power consumption.

9.6.3

WDTCSR – Watchdog Timer Control Register

• Bit 7 - WDIF: Watchdog Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config-

ured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt

handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in

SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.

• Bit 6 - WDIE: Watchdog Interrupt Enable

When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is

enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt

Mode, and the corresponding interrupt is executed if a time-out in the Watchdog Timer occurs.

If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in

the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE

and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is use-

ful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and

System Reset Mode, WDIE must be set after each interrupt. This should however not be done

within the interrupt service routine itself, as this might compromise the safety-function of the

Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a Sys-

tem Reset will be applied.

Notes: 1. WDTON is a fuse bit (see “Fuse High Byte” on page 379).

Bit

7654

$000060

WDIF

WDIE

WDP3

WDCE

WDE

WDP2

WDP1

WDP0

WDTCSR

Read/write

R/W

Initial value

0000

0x00

Table 9-6.

Watchdog Timer Configuration

WDTON(1)

WDE

WDIE

Mode

Action on Time-out

Stopped

None

Interrupt Mode

Interrupt

System Reset Mode

Reset

Interrupt and System Reset

Mode

Interrupt, then go to System

Reset Mode

System Reset Mode

Reset

AT90SCR100 데이터시트(PDF) 61 Page - ATMEL Corporation

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