AT90SCR100 datasheet(62/433 Pages) ATMEL

62 / 433 page

TPR0327AY–SMS–30Jan09

AT90SCR100

• Bit 4 - WDCE: Watchdog Change Enable

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit,

and/or change the prescaler bits, WDCE must be set.

Once written to one, hardware will clear WDCE after four clock cycles.

• Bit 3 - WDE: Watchdog System Reset Enable

WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is

set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during con-

ditions causing failure, and a safe start-up after the failure.

• Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3..0

The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run-

ning. The different prescaling values and their corresponding time-out periods are shown in

Table 9-7 on page 62.

Table 9-7.

Watchdog Timer Prescale Select

WDP3

WDP2

WDP1

WDP0

Number of WDT Oscillator

Cycles

Typical Time-out at

CC = 5.0V

2K (2048) cycles

15.625 ms

4K (4096) cycles

31.25 ms

8K (8192) cycles

62.5 ms

16K (16384) cycles

0.122 s

32K (32768) cycles

0.24 s

64K (65536) cycles

0.48 s

128K (131072) cycles

0.97 s

256K (262144) cycles

1.95 s

512K (524288) cycles

3.9 s

1024K (1048576) cycles

7.81 s

010

Reserved

011

100

101

110

111

AT90SCR100 데이터시트(PDF) 62 Page - ATMEL Corporation

AT90SCR100 데이터시트(HTML) 62 Page - ATMEL Corporation

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