AT90SCR100 datasheet(72/433 Pages) ATMEL

72 / 433 page

TPR0327AY–SMS–30Jan09

AT90SCR100

rupt. The corresponding interrupt of the Pin Change Interrupt Request is executed from the PCI2

Interrupt Vector. PCINT23:16 pins are enabled individually by the PCMSK2 Register.

• Bit 1 – PCIE1 : Pin Change Interrupt Enable 1

When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 1 is enabled. Any change on any enabled PCINT15:8 pin will cause an inter-

rupt. The corresponding interrupt of the Pin Change Interrupt Request is executed from the PCI1

Interrupt Vector. PCINT15:8 pins are enabled individually by the PCMSK1 Register.

• Bit 0 – PCIE0 : Pin Change Interrupt Enable 0

When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt 0 is enabled. Any change on any enabled PCINT7:0 pin will cause an interrupt.

The corresponding interrupt of the Pin Change Interrupt Request is executed from the PCI0

Interrupt Vector. PCINT7:0 pins are enabled individually by the PCMSK0 Register.

11.1.6

PCIFR – Pin Change Interrupt Flag Register

• Bit 3– PCIF3 : Pin Change Interrupt Flag 3

When a logic change on any PCINT31:24 pin triggers an interrupt request, PCIF3 becomes set

(one). If the I-bit in SREG and the PCIE3 bit in PCICR are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

• Bit 2 – PCIF2 : Pin Change Interrupt Flag 2

When a logic change on any PCINT23:16 pin triggers an interrupt request, PCIF2 becomes set

(one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

• Bit 1 – PCIF1 : Pin Change Interrupt Flag 1

When a logic change on any PCINT15:8 pin triggers an interrupt request, PCIF1 becomes set

(one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

• Bit 0 – PCIF0 : Pin Change Interrupt Flag 0

When a logic change on any PCINT7:0 pin triggers an interrupt request, PCIF0 becomes set

(one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the

corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-

natively, the flag can be cleared by writing a logical one to it.

Bit

6543210

0x1B (0x3B)

----

PCIF3

PCIF2

PCIF1

PCIF0

PCIFR

Read/write

RRRRR

R/W

Initial value

0x00

AT90SCR100 데이터시트(PDF) 72 Page - ATMEL Corporation

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