AT90SCR100 datasheet(173/433 Pages) ATMEL

173 / 433 page

173

TPR0327AY–SMS–30Jan09

AT90SCR100

The USBDMA controller basically requires four I/O registers to run and can be configured either

to send or to receive data through the USB bus. Actually, its main purpose is to transfer data

between the RAM of the AT90SCR100 and the DPRAM of the USB module. Very easy to use, it

just requires the application software to select an endpoint (which can be the source or the des-

tination), to set a valid base address in RAM (which can be the source or the destination), to fix

the amount of data to be exchanged and the direction of the transfer.

One USBDMA operation can transfer up to N bytes in (N+1) AVR cycles.

Figure 14-6.

USBDMA Controller Diagram

14.9.1

USBDMACS - USBDMA Control and Status Register

This is the control and status register of the USBDMA controller.

• Bit 7 - Res : Reserved Bit

This bit is reserved in the AT90SCR100 and is always read as zero.

• Bit 6..4 - EPS2..0 : Endpoint Selection Bits

Even if not represented above, the exchanges between the RAM and the DPRAM

are controlled by the USB USBFI (see “USB Module Diagram” on page 34).

When a USBDMA operation is started, the AVR is automatically stopped. At the

end of the USBDMA operation, the application software automatically restarts

where it left (actually with the instruction following the launching of the USBDMA

operation). Thus the application software does not need to wait for an interruption

or to poll the end of the USBDMA operation.

RAM

DPRAM

$100

$10FF

Endpoint 0

(64 Bytes)

Endpoint 1

(2x64 Bytes)

Endpoint 2

(2x64 Bytes)

Endpoint 3

(2x64 Bytes)

USBDMACS.EPS2:0

000

001

010

011

USBDMACS.DMAR

USBDMACS.DMADIR

USBDMACS.DMAERR

DMAD

Endpoint 4

(8 Bytes)

Endpoint 5

(8 Bytes)

Endpoint 6

(8 Bytes)

100

101

110

Endpoint 7

(8 Bytes)

111

DMA Controller Diagram

Note

Bit

654

$0000EA

EPS2

EPS1

EPS0

USBDMAERR USBDMAIR USBDMAR USBDMACS

Read/write

R/W

Initial value

0x00

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