AT90SCR100 datasheet(188/433 Pages) ATMEL

188 / 433 page

188

TPR0327AY–SMS–30Jan09

AT90SCR100

As soon as the program executes the CPRES interrupt routine, the CPRES interrupt is automat-

ically cleared. See “Interrupts” on page 63 for CPRES interrupt vector address."

An internal pull-up on Card Presence input can be disconnected in order to reduce the con-

sumption (SCSR.CPRESRES). In this case, an external resistor (typically 1 M

Ω) must be

externally tied to Vcc.

15.6.3

Transmit / Receive Buffer

The contents of the SCIBUF Transmit / Receive Buffer is transferred or received into / from the

Shift Register. The Shift Register is not accessible by the microcontroller. Its role is to prepare

the byte to be copied on the I/O pin for a transmission or in the SCIBUF buffer after a reception.

During a character transmission process, as soon as the contents of the SCIBUF buffer is trans-

ferred to the shift register, the SCTBE bit is set in SCISR register to indicate that the SCIBUF

buffer is empty and ready to accept a new byte. This mechanism avoids to wait for the complete

transmission of the previous byte before writing a new byte in the buffer and enables to speed

up the transmission.

• If the Character repetition mode is not selected (bit CREP=0 in SCICR), as soon as the

contents of the Shift Register is transferred to I/O pin, the SCTC bit is set in SCISR register to

indicate that the byte has been transmitted.

• If the Character repetition mode is selected (bit CREP=1 in SCICR) The terminal will be able

to repeat characters as requested by the ICC (See the Parity Error in T=0 protocol

description in the definition paragraph above). The SCTC bit in SCISR register will be set

after a successful transmission (no retry or no further retry requested by the ICC). If the

number of retries is exhausted (up to 4 retries depending on CREPSEL bit in SCSR) and the

last attempt is still unsuccessful, the SCTC bit in SCISR will not be set and the SCPE bit in

SCISR register will be set instead.

During a character reception process, the contents of the Shift Register is transferred in the SCI-

BUF buffer.

• If the Character repetition mode is not selected (bit CREP=0 in SCICR), as soon as the

contents of the Shift Register is transferred to the SCIBUF the SCRC bit is set in SCISR

character ready to be read by the microcontroller.

• If the Character repetition mode is selected (bit CREP=1 in SCICR) The terminal will be able

to request repetition if the received character exhibit a parity error. Up to 4 retries can be

requested depending on CREPSEL bit in SCSR. The SCRC bit will be set in SCISR register

after a successful reception, first reception or after retry(ies). If the number of retries is

exhausted (up to 4 retries depending on CREPSEL bit in SCSR) and the last retry is still

If Card Presence interruption is enabled, the AT90SCR100 wakes up from low

power mode as soon as an event on CPRES is detected.

Note

AT90SCR100 데이터시트(PDF) 188 Page - ATMEL Corporation

AT90SCR100 데이터시트(HTML) 188 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL