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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AT90SCR100 데이터시트(PDF) 199 Page - ATMEL Corporation |
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AT90SCR100 데이터시트(HTML) 199 Page - ATMEL Corporation |
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199 / 433 page  199 TPR0327AY–SMS–30Jan09 AT90SCR100 • Bit 8..0 – GT8..0: Transmit Guard Time The minimum time between two consecutive start bits in transmit mode is GT[8:0] x ETU. This is equal to ISO IEC Guard Time +10. See “Block Guard Time Counter” on page 181. According to ISO IEC 7816, the time between 2 consecutive leading edge start bits can be set between 11 and 266 (11 to 254+12 ETUs). 15.7.10 SCWT - Smart Card Character/Block Waiting Time Register • Bit 31..0 – WT: Waiting Time Byte WT[31:0] is the reload value of the Waiting Time Counter (WTC). The WTC is a general-purpose timer. It uses the ETU clock and is controlled by the WTEN bit (See “SCICR - Smart Card Interface Control Register” on page 190. and See “Waiting Time (WT) Counter” on page 183.). When UART bit of “Smart Card Interface Block Registers” is set, the WTC is automatically reloaded at each start bit of the UART. It is used to check the maximum time between to consec- utive start bits. 15.7.11 SCICLK - Smart Card Clock Register • Bit 7..6 – Reserved Bits These bits are reserved for future use. • Bit 5..0 – SCICLK5..0: Clock Bits Combination of SCICLK bits provide clock divider for Smart Card Interface output as follow: Bit 7 6543 2 1 0 $0000F4 WT [31..24] SCWT3 $0000F3 WT (23..16] SCWT2 $0000F2 WT [15..8] SCWT1 $0000F1 WT [7..0] SCWT0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 0x00 0 0000 0 0 0 0x00 0 0100 1 0 1 0x25 1 0000 0 0 0 0x80 If SCICR.WTEN=0, the Waiting Time Counter is loaded by writting SCWT2 and resetting SCICR.WTEN. Caution ! Bit 7 6 5 4 3 2 1 0 $0000F0 - - SCICLK [5..0] SCICLK Read/write R R R/W R/W R/W R/W R/W R/W Initial value 0 0 1 0 1 1 1 1 0x2F |
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