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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AT90SCR100 데이터시트(PDF) 214 Page - ATMEL Corporation |
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AT90SCR100 데이터시트(HTML) 214 Page - ATMEL Corporation |
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214 / 433 page  214 TPR0327AY–SMS–30Jan09 AT90SCR100 Figure 17-7. Example of OUT Data bank Management 17.5.12.2 “Autoswitch” mode In this mode, the clear of the UPINTX.FIFOCON bit is performed automatically by hardware each time the Pipe bank is full. The firmware has to check if the next bank is empty or not before writing the next data. On UPINTX.TXOUTI interrupt, the firmware fills a complete bank. A new interrupt will be generated each time the current bank becomes free. OUT ACK DATA (Bank 0) UPINTX.TXOUTI SW SW UPINTX.FIFOCON SW SW OUT Write data from CPU Bank 0 Write data from CPU Bank 0 HW OUT OUT ACK ACK DATA (Bank 0) DATA (Bank 1) UPINTX.TXOUTI SW SW UPINTX.FIFOCON SW SW Write data from CPU Bank 0 SW Write data from CPU Bank 1 Write data from CPU Bank 0 HW Example with 1 OUT data bank Example with 2 OUT data banks OUT OUT ACK ACK DATA (Bank 0) DATA (Bank 1) UPINTX.TXOUTI SW SW UPINTX.FIFOCON SW SW Write data from CPU Bank 0 SW Write data from CPU Bank 1 Write data from CPU Bank 0 HW Example with 2 OUT data banks |
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