AT90SCR100 datasheet(240/433 Pages) ATMEL

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TPR0327AY–SMS–30Jan09

AT90SCR100

When the Data Register Empty Interrupt Enable (UDRIE0) bit in UCSR0B is written to one, the

USART Data Register Empty Interrupt will be executed as long as UDRE0 is set (assuming that

global interrupts are enabled). UDRE0 is cleared by writing UDR0. When interrupt-driven data

transmission is used, the Data Register Empty interrupt routine must either write new data to

UDR0 in order to clear UDRE0 or disable the Data Register Empty interrupt, otherwise a new

interrupt will occur once the interrupt routine terminates.

The Transmit Complete (TXC0) Flag bit is set when the entire frame in the Transmit Shift Regis-

ter has been shifted out and there are no new data currently present in the transmit buffer. The

TXC0 Flag bit is automatically cleared when a transmit complete interrupt is executed, or it can

be cleared by writing a one to its bit location. The TXC0 Flag is useful in half-duplex communica-

tion interfaces (like the RS-485 standard), where a transmitting application must enter receive

mode and free the communication bus immediately after completing the transmission.

When the Transmit Compete Interrupt Enable (TXCIE0) bit in UCSR0B is set, the USART

Transmit Complete Interrupt will be executed when the TXC0 Flag becomes set (provided that

global interrupts are enabled). When the transmit complete interrupt is used, the interrupt han-

dling routine does not have to clear the TXC0 Flag, this is done automatically when the interrupt

is executed.

18.7.4

Parity Generator

The Parity Generator calculates the parity bit for the serial frame data. When parity bit is enabled

(UPM01 = 1), the transmitter control logic inserts the parity bit between the last data bit and the

first stop bit of the frame that is sent.

18.7.5

Disabling the Transmitter

The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongo-

ing and pending transmissions are completed, i.e., when the Transmit Shift Register and

Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter

will no longer override the TxD0 pin.

18.8

Data Reception – The USART Receiver

The USART Receiver is enabled by writing the Receive Enable (RXEN0) bit in the UCSR0B

ridden by the USART and given the function as the Receiver’s serial input. The baud rate, mode

of operation and frame format must be set up once before any serial reception can be done. If

synchronous operation is used, the clock on the XCK pin will be used as transfer clock.

18.8.1

Receiving Frames with 5 to 8 Data Bits

The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start

bit will be sampled at the baud rate or XCK clock, and shifted into the Receive Shift Register until

the first stop bit of a frame is received. A second stop bit will be ignored by the Receiver. When

the first stop bit is received, i.e., a complete serial frame is present in the Receive Shift Register,

the contents of the Shift Register will be moved into the receive buffer. The receive buffer can

then be read by reading the UDR0 I/O location.

The following code example shows a simple USART receive function based on polling of the

Receive Complete (RXC0) Flag. When using frames with less than eight bits the most significant

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