AT90SCR100 datasheet(249/433 Pages) ATMEL

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249

TPR0327AY–SMS–30Jan09

AT90SCR100

18.11 USART Register Description

18.11.1

UDR0 – USART I/O Data Register n

The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the

same I/O address referred to as USART Data Register or UDR0. The Transmit Data Buffer Reg-

ister (TXB) will be the destination for data written to the UDR0 Register location. Reading the

UDR0 Register location will return the contents of the Receive Data Buffer Register (RXB).

For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to

zero by the Receiver.

The transmit buffer can only be written when the UDRE0 Flag in the UCSR0A Register is set.

Data written to UDR0 when the UDRE0 Flag is not set, will be ignored by the USART Transmit-

ter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter

will load the data into the Transmit Shift Register when the Shift Register is empty. Then the

data will be serially transmitted on the TxD0 pin.

The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the

receive buffer is accessed. Due to this behavior of the receive buffer, do not use Read-Modify-

Write instructions (SBI and CBI) on this location. Be careful when using bit test instructions

(SBIC and SBIS), since these also will change the state of the FIFO.

18.11.2

UCSR0A – USART Control and Status Register A

• Bit 7 – RXC0: USART Receive Complete

This flag bit is set when there are unread data in the receive buffer and cleared when the receive

buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive

buffer will be flushed and consequently the RXC0 bit will become zero. The RXC0 Flag can be

used to generate a Receive Complete interrupt (see description of the RXCIE0 bit).

• Bit 6 – TXC0: USART Transmit Complete

This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and

there are no new data currently present in the transmit buffer (UDR0). The TXC0 Flag bit is auto-

matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing

a one to its bit location. The TXC0 Flag can generate a Transmit Complete interrupt (see

description of the TXCIE0 bit).

• Bit 5 – UDRE0: USART Data Register Empty

Bit

7654

UDR0

$0000C6

RXB[7..0]

(Read)

$0000C6

TXB[7..0]

(Write)

Read/write

R/W

Initial value

0000

0x00

Bit

7654

$0000C0

RXC0

TXC0

UDRE0

FE0

DOR0

UPE0

U2X0

MPCM0

UCSR0A

Read/write

R/W

Initial value

0010

0x20

AT90SCR100 데이터시트(PDF) 249 Page - ATMEL Corporation

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