AT90SCR100 datasheet(367/433 Pages) ATMEL

367 / 433 page

367

TPR0327AY–SMS–30Jan09

AT90SCR100

28.5

Entering the Boot Loader Program

Entering the Boot Loader takes place by a jump or call from the application program. This may

be initiated by a trigger such as a command received via USART, or SPI interface. Alternatively,

the Boot Reset Fuse can be programmed so that the Reset Vector is pointing to the Boot Flash

start address after a reset. In this case, the Boot Loader is started after a reset. After the applica-

tion code is loaded, the program can start executing the application code. Note that the fuses

cannot be changed by the MCU itself. This means that once the Boot Reset Fuse is pro-

grammed, the Reset Vector will always point to the Boot Loader Reset and the fuse can only be

changed through the serial programming interface.

Note:

1. “1” means unprogrammed, “0” means programmed

28.5.1

SPMCSR – Store Program Memory Control and Status Register

The Store Program Memory Control and Status Register contains the control bits needed to con-

trol the Boot Loader operations.

• Bit 7 – SPMIE: SPM Interrupt Enable

If the SPMIE bit is set (one), and if the I-bit in the Status Register is set (one), the SPM ready

interrupt will be enabled.

The SPM ready Interrupt will remain activated as long as the SPMEN bit in the SPMCSR Regis-

ter is cleared (zero).

• Bit 6 – RWWSB: Read-While-Write Section Busy

When a Self-Programming (Page Erase or Page Write) operation to the RWW section is initi-

ated, the RWWSB will be set (one) by hardware.

When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be

cleared if the RWWSRE bit is written to one after a Self-Programming operation is completed.

Alternatively the RWWSB bit will automatically be cleared if a page load operation is initiated.

• Bit 5 – SIGRD: Signature Row Read

If this bit is written to one at the same time as SPMEN, the next LPM instruction within three

clock cycles will read a byte from the signature row into the destination register. see “Reading

the Signature Row from Software” on page 373 for details. An SPM instruction within four cycles

after SIGRD and SPMEN are set will have no effect. This operation is reserved for future use

and should not be used.

• Bit 4 – RWWSRE: Read-While-Write Section Read Enable

Table 28-4.

Boot Reset Fuse(1)

BOOTRST

Reset Address

Reset Vector = Application Reset (address 0x0000)

Reset Vector = Boot Loader Reset (see Table 28-7 on page 376)

Bit

7654

0x37 (0x57)

SPMIE

RWWSB

SIGRD RWWSRE BLBSET

PGWRT

PGERS

SPMEN

SPMCSR

Read/write

R/W

Initial value

0001

0x00

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