ATtiny43U datasheet(86/182 Pages) ATMEL

86 / 182 page

8048B–AVR–03/09

ATtiny43U

for power regulation, rectification, and DAC applications. High frequency allows physically small

sized external components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the TOP value.

The counter is then cleared at the following timer clock cycle. The timing diagram for the fast

PWM mode is shown in Figure 12-6 on page 86. The TCNTn value is in the timing diagram

shown as a histogram for illustrating the single-slope operation. The diagram includes non-

inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes repre-

sent Compare Matches between OCRnx and TCNTn.

Figure 12-6. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OCnx pins.

Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output

can be generated by setting the COMnx1:0 to three: Setting the COMnA1:0 bits to one allowes

the OCnA pin to toggle on Compare Matches if the WGMn2 bit is set. This option is not available

for the OCnB pin (See Table 12-3 on page 91). The actual OCnx value will only be visible on the

port pin if the data direction for the port pin is set as output. The PWM waveform is generated by

setting (or clearing) the OCnx Register at the Compare Match between OCRnx and TCNTn, and

clearing (or setting) the OCnx Register at the timer clock cycle the counter is cleared (changes

from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCRnA Register represents special cases when generating a PWM

waveform output in the fast PWM mode. If the OCRnA is set equal to BOTTOM, the output will

be a narrow spike for each MAX+1 timer clock cycle. Setting the OCRnA equal to MAX will result

TCNTn

OCRnx Update and

TOVn Interrupt Flag Set

Period

OCn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Interrupt Flag Set

OCnxPWM

clk_I/O

N 256

⋅

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ATtiny43U 데이터시트(PDF) 86 Page - ATMEL Corporation