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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ATtiny43U 데이터시트(PDF) 89 Page - ATMEL Corporation |
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ATtiny43U 데이터시트(HTML) 89 Page - ATMEL Corporation |
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89 / 182 page  89 8048B–AVR–03/09 Figure 12-8. Timer/Counter Timing Diagram, no Prescaling Figure 12-9 on page 89 shows the same timing data, but with the prescaler enabled. Figure 12-9. Timer/Counter Timing Diagram, with Prescaler (f clk_I/O/8) Figure 12-10 on page 89 shows the setting of OCFnB in all modes and OCFnA in all modes except CTC mode and PWM mode, where OCRnA is TOP. Figure 12-10. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f clk_I/O/8) Figure 12-11 on page 90 shows the setting of OCFnA and the clearing of TCNTn in CTC mode and fast PWM mode where OCRnA is TOP. clk Tn (clk I/O/1) TOVn clk I/O TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 clk I/O clk Tn (clk I/O/8) OCFnx OCRnx TCNTn OCRnx Value OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 clk I/O clk Tn (clk I/O/8) |
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