ATtiny43U datasheet(111/182 Pages) ATMEL

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8048B–AVR–03/09

Note that even when no wire mode is selected (USIWM[1:0] = 0) both the external data input

(DI/SDA) and the external clock input (USCK/SCL) can still be used by the USI Data Register.

The output pin (DO or SDA, depending on the wire mode) is connected via the output latch to

the most significant bit (bit 7) of the USI Data Register. The output latch ensures that data input

is sampled and data output is changed on opposite clock edges. The latch is open (transparent)

during the first half of a serial clock cycle when an external clock source is selected (USICS1 =

1) and constantly open when an internal clock source is used (USICS1 = 0). The output will be

changed immediately when a new MSB is written as long as the latch is open.

Note that the Data Direction Register bit corresponding to the output pin must be set to one in

order to enable data output from the USI Data Register.

14.5.4

USIBR – USI Data Buffer

Instead of reading data from the USI Data Register the USI Buffer Register can be used. This

makes controlling the USI less time critical and gives the CPU more time to handle other pro-

gram tasks. USI flags as set similarly as when reading the USIDR register.

The content of the USI Data Register is loaded to the USI Buffer Register when the transfer has

been completed.

Bit

0x10 (0x30)

MSB

LSB

USIBR

Read/Write

Initial Value

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