AS3524 datasheet(71/124 Pages) AMSCO

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AS3524 C21 / C22

austriamicrosystems

Data Sheet, Confidential

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Revision 1.11

- 124

Table 49 NAF FiFo Data register

Name

Base

Default

NAFFifodata

AS3525_NAND_FLASH_BASE

0x0000

FIFO Data Register

Offset 0x001c

The NAFFifodata register offers access to the internal FIFO.

Bit

Bit Name

Default

Access

Bit Description

32:0

Fifodata [32:0]

R/W

Writing this register will push a word on the FIFO and the write

address will be incremented by 1. When the FIFO is full (36

words) then a write access on the register is ignored and the

FIFO ERROR status bit is set.

Reading on this register will pop a word from the FIFO and the

read address will be incremented by 1. When the FIFO is

empty then a read access on the register is ignored and the

FIFO ERROR status bit is set.

Table 50 NAF interrupt mask register

Name

Base

Default

NAFWords

AS3525_NAND_FLASH_BASE

0x0000

Interrupt Mask Register

Offset 0x0020

The NAFWords register informs the controller about the maximum words to be

transferred and controls the FIFO transfer both in interrupt and DMA mode.

Bit

Bit Name

Default

Access

Bit Description

32:0

Words [32:0]

0x0000

R/W

0: FIFO based data transfer is disabled

not 0: FIFO transfer is in progress

Note: For page transfers (program or read) the initial number of words depends on the NAND flash device. For a page size of 512 bytes, an initial

word value of 512/4 = 128 has to be written. For a page size of 2k bytes, an initial word value of 512 has to be used.

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