AS3524 datasheet(52/124 Pages) AMSCO

52 / 124 page

AS3524 C21 / C22

austriamicrosystems

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.11

- 124

Table 32 I2S input status register

Name

Base

Default

I2SIN_STATUS

AS3525_I2SIN_BASE

0x00

Status register

Offset: 0x000C

The status register is a read-only register. A read to this register returns the value

of the raw status bits AND’ed with the corresponding mask of enable bits set in the

mask register.

Bit

Bit Name

Default

Access

Bit Description

stereo24_status

Status of write interface for 24 bit stereo mode

0: left audio sample will be transferred next

1: right audio sample will be transferred next

I2SIN_PUER

1 if FIFO PUSH error

I2SIN_POE

1 if FIFO POP is empty

I2SIN_POAE

1 if FIFO POP is almost empty

I2SIN_POHF

1 if FIFO POP is half full

I2SIN_POAF

1 if FIFO POP is almost full

I2SIN_POF

1 if FIFO POP is full

I2SIN_POER

1 if FIFO POP error

Table 33 I2S Input interrupt clear register

Name

Base

Default

I2SIN_CLEAR

AS3525_I2SIN_BASE

0x00

Interrupt clear register

Offset: 0x0010

The interrupt clear register is a write-only register. The corresponding static status

bit can be cleared by writing a 1 to the corresponding bit in the clear register. All

other interrupt flags are level interrupts depending on the status of the FIFO. The

bits are de-asserted depending on the FIFO controller.

Bit

Bit Name

Default

Access

Bit Description

reserved

I2SIN_clear_puer

Clear PUSH error interrupt flag

5:1

reserved

I2SIN_clear_poer

Clear POP error interrupt flag

I2SIN_DATA

The I2SINIF provides a single 32 bit wide data register. The register is used to read the audio samples from FIFO. If 14

bit mode is selected, both the left and right data are made available in the same register. Otherwise in the 24 bit mode

the left and right data are provided through the same register alternatively. The stereo24_status bit in the I2SIN_STATUS

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