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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AS3524 데이터시트(PDF) 94 Page - ams AG |
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AS3524 데이터시트(HTML) 94 Page - ams AG |
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94 / 124 page  AS3524 C21 / C22 austriamicrosystems Data Sheet, Confidential © 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.11 94 - 124 Table 72 Setting the PLL output frequency Input divider NR. NR = 16 * R4 + 8*R3 + 4*R2 + 2*R1 + R0 Feedback divider NF: NF = 2 * (128*F7 + 64*F6 + 32*F5 + 16*F4 + 8*F3 + 4*F2 + 2*F1 + F0 Output divider NO: Output divider setting NO (output divider value) OD0=0, OD1=0 Not allowed OD0=1, OD1=0 1 OD0=0, OD1=1 2 OD0=1, OD1=1 4 The PLL output frequency is calculated with following formula Output frequency in out f NO NR NF f ⋅ ⋅ = Comparison frequency NR f f in ref = VCO frequency in vco f NR NF f ⋅ = Following constraints must be followed for the comparison and output frequency: MHz fVCO MHz MHz fref MHz 400 200 8 2 ≤ ≤ ≤ ≤ |
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