AS3524 datasheet(89/124 Pages) AMSCO

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AS3524 C21 / C22

austriamicrosystems

Data Sheet, Confidential

www.austriamicrosystems.com

Revision 1.11

- 124

Table 70 UART Line status register

Name

Base

Default

UART_LNSTATUS_REG

AS3525_UART_BASE

0xC8110000

Line status register

Offset: 0x14

This register holds the status information of the data transfer. It gives information about

the received data.

Bit

Bit Name

Default

Access

Bit Description

FIFODataError

1: This bit is set when any data character in the FIFO has

parity or framing error or break condition.

0: This bit is reset once the line status register

(LINE_STATUS_REG) is read.

Reserved

This bit is reserved for future use.

txHoldRegEmpty

This bit is associated with the txDataEmpty interrupt.

1: Indicates that there is no data in txFIFO or the data register

(UART_DATA_REG (Tx)). This bit is set once the data is

shifted out.

0: This bit is reset once data is written into the data register

(UART_DATA_REG (Tx)).

breakDetect

This bit is associated with the rxLineStatus interrupt.

1: This bit is set if a break condition is detected, i.e. if a zero

is detected on receive line for one full character duration. This

condition will always cause framingError condition.

framingError

This bit is associated with the rxLineStatus interrupt.

1: Indicates that the first stop bit of the received data byte is

not valid, i.e. a zero is received in place of a one.

This error condition causes the receiver to re-synchronize.

parityError

This bit is associated with rxLineStatus interrupt.

1: Indicates that parity of the received data byte is different

from the expected parity as set in the line control register

(UART_LNCTL_REG).

overrunError

This bit is associated with the rxLineStatus interrupt.

1: Indicates an error condition which occurs when one

character is fully assembled by the receiver but there is no

space to write that byte.

In FIFO mode, the content of the FIFO remains unaffected.

If FIFO is disabled, the data register (UART_DATA_REG (Rx))

will be overwritten with the new data.

dataReady

0: There is no data available.

1: There are one or more data bytes ready to be read by the

processor.

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