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AS3524 데이터시트(PDF) 74 Page - ams AG

부품명 AS3524
상세설명  Advanced Audio Processor System
PDF  124 Pages
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제조업체  AMSCO [ams AG]
홈페이지  http://www.ams.com
Logo AMSCO - ams AG

AS3524 데이터시트(HTML) 74 Page - ams AG

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AS3524 C21 / C22
austriamicrosystems
Data Sheet, Confidential
© 2003-2006, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1.11
74
- 124
5.3.12.1 DBOP register definitions
Table 53 DBOP Registers
Register Name
Base Address
Offset
Note
DBOP_TIMPOL_01
AS3525_DBOP_BASE
0x00
Timing and polarity for control 0 and 1
DBOP_TIMPOL_23
AS3525_DBOP_BASE
0x04
Timing and polarity for control 1 and 2
DBOP_CTRL_REG
AS3525_DBOP_BASE
0x08
Control Register
DBOP_STAT_REG
AS3525_DBOP_BASE
0x0C
Status Register
DBOP_DOUT_REG
AS3525_DBOP_BASE
0x10
Data output register
DBOP_DIN_REG
AS3525_DBOP_BASE
0x14
Data input register
Timing & Polarity Control register TPC01
This register contains all information necessary for definition of control signals C0 and C1.
Table 54 DBOP control registers C0 and C1
Register
bits
Name
type
function
default
value
31
c1_p0
r/w
polarity 1
0
30
c1_p1
r/w
polarity 2
1
29
c1_p2
r/w
polarity 3
0
28:24
c1_t1
r/w
Time 1
0xA
23:19
c1_t2
r/w
Time 2
0x14
18
c1_ev
r/w
even enable
1
17
c1_od
r/w
odd enable
1
16
c1_qs
r/w
quiescent state
0
15
c0_p0
r/w
polarity 1
0
14
c0_p1
r/w
polarity 2
1
13
c0_p2
r/w
polarity 3
0
12:8
c0_t1
r/w
Time 1
0xA
7:3
c0_t2
r/w
Time 2
0x14
2
c0_ev
r/w
even enable
1
1
c0_od
r/w
odd enable
1
0
c0_qs
r/w
quiescent state
0
Timing & Polarity Control register TPC23
This register contains all information necessary for definition of control signals C2 and C3.
Table 55 DBOP control registers C2 and C3
Register
bits
Name
type
function
default
value
31
c3_p0
r/w
polarity 1
0
30
c3_p1
r/w
polarity 2
1
29
c3_p2
r/w
polarity 3
0
28:24
c3_t1
r/w
Time 1
0xA
23:19
c3_t2
r/w
Time 2
0x14
18
c3_ev
r/w
even enable
1
17
c3_od
r/w
odd enable
1
16
c3_qs
r/w
quiescent state
0
15
c2_p0
r/w
polarity 1
0
14
c2_p1
r/w
polarity 2
1
13
c2_p2
r/w
polarity 3
0
12:8
c2_t1
r/w
Time 1
0xA
7:3
c2_t2
r/w
Time 2
0x14
2
c2_ev
r/w
even enable
1
1
c2_od
r/w
odd enable
1
0
c2_qs
r/w
quiescent state
0



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