HCS12 datasheet(298/452 Pages) FREESCALE

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Instruction Glossary

S12CPUV2 Reference Manual, Rev. 4.0

298

Freescale Semiconductor

Operation:

(SP) – $0002

⇒ SP; RTNH : RTNL ⇒ (M(SP) : M(SP+1))

(SP) – $0002

⇒ SP; YH : YL ⇒ (M(SP) : M(SP+1))

(SP) – $0002

⇒ SP; XH : XL ⇒ (M(SP) : M(SP+1))

(SP) – $0002

⇒ SP; B : A⇒ (M(SP) : M(SP+1))

(SP) – $0001

⇒ SP; CCR ⇒ (M(SP))

⇒ I

(Trap Vector)

⇒ PC

Description:

Traps unimplemented opcodes. There are opcodes in all 256 positions in

the page 1 opcode map, but only 54 of the 256 positions on page 2 of the

opcode map are used. If the CPU attempts to execute one of the

unimplemented opcodes on page 2, an opcode trap interrupt occurs.

Unimplemented opcode traps are essentially interrupts that share the

$FFF8:$FFF9 interrupt vector.

TRAP uses the next address after the unimplemented opcode as a return

address. It stacks the return address, index registers Y and X, accumulators

B and A, and the CCR, automatically decrementing the SP before each item

is stacked. The I mask bit is then set, the PC is loaded with the trap vector,

and instruction execution resumes at that location. This instruction is not

maskable by the I bit. Refer to Section 7. Exception Processing for more

information.

TRAP

Unimplemented Opcode Trap

TRAP

CCR Details:

HIN

–––1––––

1; set

Source Form

Address

Mode

Object Code

Access Detail

HCS12

M68HC12

TRAP trapnum

INH

$18 tn

(1)

1. The value tn represents an unimplemented page 2 opcode in either of the two ranges $30 to $39 or $40 to $FF.

OVSPSSPSsP

OfVSPSSPSsP

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