HCS12 datasheet(411/452 Pages) FREESCALE

411 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

411

The M68HC11 has one variation of indexed addressing that works from X

or Y as the reference pointer. For X indexed addressing, an 8-bit unsigned

offset in the instruction is added to the index pointer to arrive at the address

of the operand for the instruction. A load accumulator instruction assembles

into two bytes of object code, the opcode and a 1-byte offset. Using Y as the

reference, the same instruction assembles into three bytes (a page prebyte,

the opcode, and a 1-byte offset.) Analysis of M68HC11 source code

indicates that the offset is most frequently zero and seldom greater than

four.

The CPU12 indexed addressing scheme uses a postbyte plus 0, 1, or 2

extension bytes after the instruction opcode. These bytes specify which

index register is used, determine whether an accumulator is used as the

offset, implement automatic pre/post increment/decrement of indices, and

allow a choice of 5-, 9-, or 16-bit signed offsets. This approach eliminates

the differences between X and Y register use and dramatically enhances

indexed addressing capabilities.

Major improvements that result from this new approach are:

• Stack pointer can be used as an index register in all indexed

operations (very important for C compilers)

• Program counter can be used as index register in all but auto inc/dec

modes

• Accumulator offsets allowed using A, B, or D accumulators

• Automatic pre- or post- increment or decrement by –8 to +8

• 5-bit, 9-bit, or 16-bit signed constant offsets (M68HC11 only

supported positive unsigned 8-bit offsets)

• 16-bit offset indexed-indirect and accumulator D offset

indexed-indirect

The change completely eliminates pages three and four of the M68HC11

opcode map and eliminates almost all instructions from page two of the

opcode map. For offsets of 0 to +15 from the X index register, the object

code is the same size as it was for the M68HC11. For offsets of 0 to +15

from the Y index register, the object code is one byte smaller than it was for

the M68HC11.

Table A-3 and Table A-4 summarize CPU12 indexed addressing mode

capabilities. Table A-6 shows how the postbyte is encoded.

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