HCS12 datasheet(413/452 Pages) FREESCALE

413 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

413

B.6.2 Auto-Increment Indexing

The CPU12 provides greatly enhanced auto increment and decrement

modes of indexed addressing. In the CPU12, the index modification may be

specified for before the index is used (pre-), or after the index is used (post-),

and the index can be incremented or decremented by any amount from one

to eight, independent of the size of the operand that was accessed. X, Y,

and SP can be used as the index reference, but this mode does not allow

PC to be the index reference (this would interfere with proper program

execution).

This addressing mode can be used to implement a software stack structure

or to manipulate data structures in lists or tables, rather than manipulating

bytes or words of data. Anywhere an M68HC11 program has an increment

or decrement index register operation near an indexed mode instruction, the

increment or decrement operation can be combined with the indexed

instruction with no cost in object code size, as shown in the following code

comparison.

The M68HC11 object code requires seven bytes, while the CPU12 requires

only two bytes to accomplish the same functions. Three bytes of M68HC11

code were due to the page prebyte for each Y-related instruction ($18).

CPU12 post-increment indexing capability allowed the two INY instructions

to be absorbed into the LDAA indexed instruction. The replacement code is

not identical to the original 3-instruction sequence because the Z condition

code bit is affected by the M68HC11 INY instructions, while the Z bit in the

CPU12 would be determined by the value loaded into A.

18 A6 00

18 08

LDAA 0,Y

INY

LDAA

2,Y+

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