HCS12 datasheet(417/452 Pages) FREESCALE

417 / 452 page

S12CPUV2 Reference Manual, Rev. 4.0

Freescale Semiconductor

417

instructions replace whole subroutines in the M68HC11 version. Table

lookup instructions also greatly reduce code space.

Other CPU12 code space reductions are more subtle. Memory-to- memory

moves are one example. The CPU12 move instruction requires almost as

many bytes as an equivalent sequence of M68HC11 instructions, but the

move operations themselves do not require the use of an accumulator. This

means that the accumulator often need not be saved and restored, which

saves instructions.

Arithmetic operations on index pointers are another example. The

M68HC11 usually requires that the content of the index register be moved

into accumulator D, where calculations are performed, then back to the

index register before indexing can take place. In the CPU12, the LEAS,

LEAX, and LEAY instructions perform arithmetic operations directly on the

index pointers. The pre-/post-increment/decrement variations of indexed

addressing also allow index modification to be incorporated into an existing

indexed instruction rather than performing the index modification as a

separate operation.

Transfer and exchange operations often allow register contents to be

temporarily saved in another register rather than having to save the

contents in memory. Some CPU12 instructions such as MIN and MAX

combine the actions of several M68HC11 instructions into a single

operation.

B.8 Additional Functions

The CPU12 incorporates a number of new instructions that provide added

functionality and code efficiency. Among other capabilities, these new

instructions allow efficient processing for fuzzy logic applications and

support subroutine processing in extended memory beyond the standard

64-Kbyte address map for M68HC12 devices incorporating this feature.

Table B-4 is a summary of these new instructions. Subsequent paragraphs

discuss significant enhancements.

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