HCS12 datasheet(184/452 Pages) FREESCALE

184 / 452 page

Instruction Glossary

S12CPUV2 Reference Manual, Rev. 4.0

184

Freescale Semiconductor

Operation:

(Counter) + 1

⇒ Counter

If (Counter) = 0, then (PC) + $0003 + Rel

⇒ PC

Description:

Add one to the specified counter register A, B, D, X, Y, or SP. If the counter

IBEQ instruction is encoded into three bytes of machine code including a

9-bit relative offset (–256 to +255 locations from the start of the next

instruction).

DBEQ and TBEQ instructions are similar to IBEQ except that the counter is

decremented or tested rather than being incremented. Bits 7 and 6 of the

instruction postbyte are used to determine which operation is to be

performed.

IBEQ

Increment and Branch if Equal to Zero

IBEQ

CCR Details:

HIN

––––––––

Source Form

Address

Mode

Object Code(1)

1. Encoding for lb is summarized in the following table. Bit 3 is not used (don’t care), bit 5 selects branch on zero (IBEQ –

0) or not zero (IBNE – 1) versions, and bit 0 is the sign bit of the 9-bit relative offset. Bits 7 and 6 should be 1:0 for IBEQ.

Access Detail

HCS12

M68HC12

IBEQ abdxys, rel9

REL

04 lb rr

PPP/PPO

PPP

Count

Bits 2:0

Source Form

Object Code

(If Offset is Positive)

Object Code

(If Offset is Negative)

000

001

IBEQ A, rel9

IBEQ B, rel9

04 80 rr

04 81 rr

04 90 rr

04 91 rr

100

101

110

111

IBEQ D, rel9

IBEQ X, rel9

IBEQ Y, rel9

IBEQ SP, rel9

04 84 rr

04 85 rr

04 86 rr

04 87 rr

04 94 rr

04 95 rr

04 96 rr

04 97 rr

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