HCS12 datasheet(188/452 Pages) FREESCALE

188 / 452 page

Instruction Glossary

S12CPUV2 Reference Manual, Rev. 4.0

188

Freescale Semiconductor

Operation:

(M) + $01

⇒ M

Description:

Add one to the content of memory location M.

The N, Z and V status bits are set or cleared according to the results of the

operation. The C status bit is not affected by the operation, thus allowing the

INC instruction to be used as a loop counter in multiple-precision

computations.

When operating on unsigned values, only BEQ, BNE, LBEQ, and LBNE

branches can be expected to perform consistently. When operating on two’s

complement values, all signed branches are available.

INC

Increment Memory

INC

CCR Details:

HIN

––––

∆∆∆

–

N: Set if MSB of result is set; cleared otherwise

Z: Set if result is $00; cleared otherwise

V: Set if there is a two’s complement overflow as a result of the

operation; cleared otherwise. Two’s complement overflow occurs if

and only if (M) was $7F before the operation.

Source Form

Address

Mode

Object Code

Access Detail

HCS12

M68HC12

INC opr16a

INC oprx0_xysp

INC oprx9,xysp

INC oprx16,xysp

INC [D,xysp]

INC [oprx16,xysp]

EXT

IDX

IDX1

IDX2

[D,IDX]

[IDX2]

72 hh ll

62 xb

62 xb ff

62 xb ee ff

62 xb

62 xb ee ff

rPwO

rPw

rPwO

frPwP

fIfrPw

fIPrPw

rOPw

rPw

rPOw

frPPw

fIfrPw

fIPrPw

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