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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HCS12 데이터시트(PDF) 190 Page - Freescale Semiconductor, Inc |
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HCS12 데이터시트(HTML) 190 Page - Freescale Semiconductor, Inc |
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190 / 452 page  Instruction Glossary S12CPUV2 Reference Manual, Rev. 4.0 190 Freescale Semiconductor Operation: (B) + $01 ⇒ B Description: Add one to the content of accumulator B. The N, Z, and V status bits are set or cleared according to the results of the operation. The C status bit is not affected by the operation, thus allowing the INC instruction to be used as a loop counter in multiple-precision computations. When operating on unsigned values, only BEQ, BNE, LBEQ, and LBNE branches can be expected to perform consistently. When operating on two’s complement values, all signed branches are available. INCB Increment B INCB CCR Details: S X HIN Z V C –––– ∆∆∆ – N: Set if MSB of result is set; cleared otherwise Z: Set if result is $00; cleared otherwise V: Set if there is a two’s complement overflow as a result of the operation; cleared otherwise. Two’s complement overflow occurs if and only if (B) was $7F before the operation. Source Form Address Mode Object Code Access Detail HCS12 M68HC12 INCB INH 52 O O |
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