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TLK6002 데이터시트(PDF) 45 Page - Texas Instruments

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부품명 TLK6002
상세설명  Dual Channel 0.47Gbps to 6.25Gbps Multi-Rate Transceiver
PDF  96 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
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TLK6002 데이터시트(HTML) 45 Page - Texas Instruments

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TLK6002
www.ti.com
SLLSE34 – MAY 2010
Table 3-1. GLOBAL_CONTROL_1 (continued)
Address: 0x00
Default: 0x0600
BIT(s)
NAME
DESCRIPTION
ACCESS
0.2
RETIME_EN
In this mode, serial A input data is sent to both the Parallel A output and Serial B output
RW
interface. Serial B input data is sent to both the Parallel B output and Serial A output
interface.
0 =
Normal functional mode (Default 1’b0)
1 =
Enable retime mode
Serial A input data rate must match (0 ppm) channel B reference clock.
Serial B input data rate must match (0 ppm) channel A reference clock
See Figure 2-11
0.1
REFCLK_A_SEL
Channel A Reference clock selection. Logically OR’ed with REFCLK_A_SEL pin.
RW
0 =
Selects REFCLK_0_P/N as clock reference to Channel A serdes macro (Default
1’b0)
1 =
Selects REFCLK_1_P/N as clock reference to Channel A serdes macro
See Figure 1-3
0.0
REFCLK_B_SEL
Channel B Reference clock selection. Logically OR’ed with REFCLK_B_SEL pin.
RW
0 =
Selects REFCLK_0_P/N as clock reference to Channel B serdes macro (Default
1’b0)
1 =
Selects REFCLK_1_P/N as clock reference to Channel B serdes macro
See Figure 1-3
Table 3-2. CHANNEL_CONTROL_1
Address: 0x01
Default: 0x010D
BIT(s)
NAME
DESCRIPTION
ACCESS
1.15
POWERDOWN
Setting this bit high powers down the SERDES datapath channel with exception that MDIO
RW
interface stays active. Logically OR’ed with inverse of PD_TRXx_N.
0 =
Normal operation (Default 1’b0)
1 =
Power Down mode is enabled.
1.10
RESERVED
For TI use only.
1.9:8
LOOP_BANDWIDTH
Serdes PLL Loop Bandwidth settings
RW
00 =
Reserved
01 =
Applicable when external JC_PLL is NOT used (Default 2’b01)
10 =
Applicable when external JC_PLL is used
11 =
Reserved
1.7:6
RATE_TX [1:0]
Serdes TX rate settings
RW
00 =
Full rate (Default 2’b00)
01 =
Half rate
10 =
Quarter rate
11 =
Eighth rate
Values written are valid only when RATE_A/B[2:0] pins are set to 3’b100 and ARS is not
enabled (10.13:12 = 2’b00)
In ARS mode, values written to these bits are not considered to determine serdes TX rate.
Instead it is automatically determined by ARS machine.
When read, these bits will reflect the final serdes Tx rate values
Copyright © 2010, Texas Instruments Incorporated
PROGRAMMERS REFERENCE
45
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Product Folder Link(s): TLK6002



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