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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TLK6002 데이터시트(PDF) 90 Page - Texas Instruments |
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TLK6002 데이터시트(HTML) 90 Page - Texas Instruments |
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90 / 96 page  TLK6002 SLLSE34 – MAY 2010 www.ti.com 8 Appendix D – Device Latency Specification The following tables show the absolute device latency in each operation mode. Table 8-1. Device Absolute Transmit Latency – SDR and DDR Modes SDR TRANSMIT ABSOLUTE LATENCY (Serial Bit Times) Note: TX FIFO, in register 6.14:12, defaults to Auto Selection Mode. This table contains latencies when the TX FIFO is set in the minimum latency mode (6.14:12 = 3'b000). LATENCY COMPONENTS Item Minimum Maximum Description A 8 12 Sampling edge of TXCLK_* to TX FIFO Input Register B 10 40 TX FIFO Input Register to TX FIFO Output Register C 20 20 TX FIFO Output Register to 8b/10b Encoder Register D 10 10 8b/10b Encoder Register to PMA Retime Register E 20 20 PMA Retime Register to TX SERDES Input Register F 16 22 TX SERDES Input Register to Serialized Output Bit Bit Detail Latency Minimum Maximum Assumption: TX*_[19] is first transmitted bit. TX*_[19:10] is first transmitted symbol. 8b/10b encoder is enabled. Disabling 8b/10b encoder reduces latency TX*_[19] 0 84 124 by 10 bit times. TX*_[10] 9 93 133 TX*_[9] 10 94 134 TX*_[0] 19 103 143 Latency Encoder Enabled Encoder Disabled Summary Minimum Maximum Minimum Maximum TX*_[19] 84 124 74 114 TX*_[10] 93 133 83 123 TX*_[9] 94 134 84 124 TX*_[0] 103 143 93 133 DDR TRANSMIT ABSOLUTE LATENCY (Serial Bit Times) DDR Transmit Latency is the same as transmit SDR mode, except that all numbers are 8 to12 bit times larger. Latency Encoder Enabled Encoder Disabled Summary Minimum Maximum Minimum Maximum TX*_[19] 92 136 82 126 TX*_[10] 101 145 91 135 TX*_[9] 102 146 92 136 TX*_[0] 111 155 101 145 90 Appendix D – Device Latency Specification Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TLK6002 |
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