TLK6002 datasheet(48/96 Pages) TI

48 / 96 page

TLK6002

SLLSE34 – MAY 2010

www.ti.com

Table 3-7. AC Mode Output Swing Control

VALUE

AC MODETYPICAL AMPLITUDE

2[3:0]

(mVdfpp)

0000

126

0001

215

0010

303

0011

395

0100

478

0101

572

0110

662

0111

756

1000

839

1001

932

1010

1020

1011

1110

1100

1190

1101

1280

1110

1360

1111

1450

Table 3-8. CHANNEL_CONTROL_3

Address: 0x03

Default: 0x0180

BIT(s)

NAME

DESCRIPTION

ACCESS

3.12:11 CH_SYNC_HYSTERESIS

Valid only when comma detection (channel synchronization) is enabled.

[1:0]

00 =

The channel synchronization, when in the synchronization state, performs the

Ethernet standard specified hysteresis to return to the unsynchronized state

(Default 2’b00)

01 =

A single 8b/10b invalid decode error or disparity error causes the channel

synchronization state machine to immediately transition from sync to unsync

10 =

Two adjacent 8b/10b invalid decode errors or disparity errors cause the channel

synchronization state machine to immediately transition from sync to unsync

11 =

Three adjacent 8b/10b invalid decode errors or disparity errors cause the

channel synchronization state machine to immediately transition from sync to

unsync

3.10

TX_SWAP_SEL

0 =

Selects same channel Tx parallel interface input data as core input data for that

channel (Default 1’b0)

1 =

Selects partner channel Tx parallel interface input data as core input data for

that channel

See Figure 1-4

3.9

RX_SWAP_SEL

0 =

Selects same channel deserialized input data to be sent out the Rx parallel

output interface (Default 1’b0)

1 =

Selects partner channel deserialized input data to be sent out the Rx parallel

output interface

See Figure 1-5

3.8

RXCLK_OUT_SEL

Parallel output clock (RXCLK_x) selection

When RX_SWAP_SEL (3.9) is 1’b0

0 =

Selects respective channel SERDES TXBCLK clock

1 =

Selects respective channel SERDES RXBCLK clock (Default 1’b1)

When RX_SWAP_SEL (3.9) is 1’b1

0 =

Selects partner channel SERDES TXBCLK clock

1 =

Selects partner channel SERDES RXBCLK clock (Default 1’b1)

See Figure 1-5

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