TLK6002 datasheet(18/96 Pages) TI

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TLK6002

SLLSE34 – MAY 2010

www.ti.com

Table 2-5. OBSAI Line Rate Selection(1)

LINE RATE

SERDES PLL

RATE SELECT (PINS OR

TXCLK_A/B

REFCLKP/N

(Mbps)

MULTIPLIER VALUE

(MHz)

6144.00

20/25

Full

307.2

153.60/122.88

3072.00

20/25

Half

153.6

153.60/122.88

1536.00

20/25

Quarter

76.8

153.60/122.88

768.00

20/25

Eighth

38.4

153.60/122.88

(1)

In DDR mode TX_CLK frequencies will be half the values in the table above. The table above indicate two possible REFCLK

frequencies, 153.60MHz and 122.88MHz which can be used based on the application preference. The Serdes PLL Multiplier (MPY) has

been given for each REFCLK frequency respectively. Note that Channel A and B are independent, and their application rates and

references clocks are separate.

2.4

Parallel Interface Modes

2.4.1

20-bit SDR (Single Data Rate) Mode (8b/10b Encoder/Decoder Disabled)

Channel A TX: TDA_[19:0]

→ TXAP/N (using TXCLK_A). RX: RXAP/N → RDA_[19:0] (using RXCLK_A).

Channel B TX: TDB_[19:0]

→ TXBP/N (using TXCLK_B). RX: RXBP/N → RDB_[19:0] (using RXCLK_B).

20 Bits (two symbols) of already encoded (TX) or undecoded (RX) data are transferred per parallel

interface clock cycle. Symbols are defined by a group of 10 parallel bits. Note that four symbols are shown

in Figure 2-1: Data0[19:10], Data0[9:0], Data1[19:10], Data1[9:0].

Symbol Transmission Order:

When 3.5/3.4 = 0: Data0[19:10] is the first transmitted or received symbol. Data0[9:0] is next, then

Data1[19:10].

When 3.5/3.4 = 1: Data0[9:0] is the first transmitted or received symbol. Data0[19:0] is next, then

Data1[9:0].

Bit Transmission Order within a Symbol:

When 8.3/2 = 0, Data[19] or Data[9] bits are serially transmitted first or received first respectively per

symbol.

When 8.3/2 = 1, Data[10] or Data[0] bits are serially transmitted first or received first respectively per

symbol.

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