910GL datasheet(185/426 Pages) INTEL

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Integrated Graphics Device Registers (D2:F0)

(Intel® 82915G/82915GV/82915GL/ 82910GL GMCH Only)

Datasheet

185

9.1.17

CAPPOINT—Capabilities Pointer (D2:F0)

PCI Device:

Address Offset:

34h

Default Value:

D0h

Access:

Size:

8 bits

Bit

Access &

Default

Description

7:0

D0h

Capabilities Pointer Value: This field contains an offset into the function’s PCI

configuration space for the first item in the New Capabilities Linked List; the

Power Management Capabilities ID registers at address D0h.

9.1.18

INTRLINE—Interrupt Line (D2:F0)

PCI Device:

Address Offset:

3Ch

Default Value:

00h

Access:

R/W

Size:

8 bits

Bit

Access &

Default

Description

7:0

R/W

00h

Interrupt Connection: This field is used to communicate interrupt line routing

information. POST software writes the routing information into this register as it

initializes and configures the system. The value in this register indicates which

input of the system interrupt controller that the device’s interrupt pin is connected

to.

9.1.19

INTRPIN—Interrupt Pin (D2:F0)

PCI Device:

Address Offset:

3Dh

Default Value:

01h

Access:

Size:

8 bits

Bit

Access &

Default

Description

7:0

01h

Interrupt Pin: As a device that only has interrupts associated with a single

function, the IGD specifies INTA# as its interrupt pin.

01h = INTA#.

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