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PSoC® 5: CY8C53 Family Datasheet

Document Number: 001-66237 Rev. *A

Page 46 of 106

8.1 Analog Routing

The CY8C38 family of devices has a flexible analog routing

architecture that provides the capability to connect GPIOs and

different analog blocks, and also route signals between different

analog blocks. One of the strong points of this flexible routing

architecture is that it allows dynamic routing of input and output

connections to the different analog blocks. All analog routing

switches are open when the device is in sleep or hibernate mode.

For information on how to make pin selections for optimal analog

routing, refer to the application note, AN58304 - PSoC® 3 and

PSoC® 5 - Pin Selection for Analog Designs.

8.1.1 Features

Flexible, configurable analog routing architecture

16 Analog globals (AG) and two analog mux buses

(AMUXBUS) to connect GPIOs and the analog blocks

Each GPIO is connected to one analog global and one analog

mux bus

8 Analog local buses (abus) to route signals between the

different analog blocks

Multiplexers and switches for input and output selection of the

analog blocks

8.1.2 Functional Description

Analog globals (AGs) and analog mux buses (AMUXBUS)

provide analog connectivity between GPIOs and the various

analog blocks. There are 16 AGs in the CY8C38 family. The

analog routing architecture is divided into four quadrants as

shown in Figure 8-2. Each quadrant has four analog globals

(AGL[0..3], AGL[4..7], AGR[0..3], AGR[4..7]). Each GPIO is

connected to the corresponding AG through an analog switch.

The analog mux bus is a shared routing resource that connects

to every GPIO through an analog switch. There are two

AMUXBUS routes in CY8C38, one in the left half (AMUXBUSL)

and one in the right half (AMUXBUSR), as shown in Figure 8-2.

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