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CY8C53 데이터시트(PDF) 6 Page - Cypress Semiconductor

부품명 CY8C53
상세설명  Programmable System-on-Chip (PSoC) DC to 67 MHz operation
PDF  106 Pages
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제조업체  CYPRESS [Cypress Semiconductor]
홈페이지  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C53 데이터시트(HTML) 6 Page - Cypress Semiconductor

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PRELIMINARY
PSoC® 5: CY8C53 Family Datasheet
Document Number: 001-66237 Rev. *A
Page 6 of 106
Figure 2-1. 68-Pin QFN Part Pinout[3]
(GPIO) P2[6]
(GPIO) P2[7]
(SIO) P12[4]
(SIO) P12[5]
Vssb
Ind
Vboost
Vbat
Vssd
XRES
(SWDIO, GPIO) P1[0]
(SWDCK, GPIO) P1[1]
(GPIO) P1[2]
(SWV, GPIO) P1[3]
(GPIO) P1[4]
(GPIO) P1[5]
Vddio1
P0[3] (GPIO, OpAmp0-/Extref0)
P0[2] (GPIO, OpAmp0+)
P0[1] (GPIO, OpAmp0out)
P0[0] (GPIO, OpAmp2out)
P12[3] (SIO)
P12[2] (SIO)
Vssd
Vdda
Vssa
Vcca
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
P12[1] (SIO)
P12[0] (SIO)
P3[7] (GPIO, OpAmp3out)
P3[6] (GPIO, OpAmp1out)
Vddio3
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
QFN
(Top View)
Lines show Vddio
to I/O supply
association
Notes
2. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
3. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal.
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