STM32F407IE datasheet(58/154 Pages) STMICROELECTRONICS

58 / 154 page

Electrical characteristics

STM32F405xx, STM32F407xx

58/154

Doc ID 022152 Rev 1

5.3

Operating conditions

5.3.1

General operating conditions

Table 8.

Current characteristics(1)

TBD stands for “to be defined”.

Symbol

Ratings

Max.

Unit

IVDD

Total current into VDD power lines (source)

(2)

All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power

supply, in the permitted range.

TBD

IVSS

Total current out of VSS ground lines (sink)

(2)

TBD

IIO

Output current sunk by any I/O and control pin

Output current source by any I/Os and control pin

IINJ(PIN)

(3)

Negative injection disturbs the analog performance of the device. See note in Section 5.3.20: 12-bit ADC

characteristics.

Injected current on five-volt tolerant I/O(4)

Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must

never be exceeded. Refer to Table 7 for the values of the maximum allowed input voltage.

–5/+0

Injected current on any other pin(5)

A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must

never be exceeded. Refer to Table 7 for the values of the maximum allowed input voltage.

±5

ΣIINJ(PIN)(5)

Total injected current (sum of all I/O and control pins)(6)

When several inputs are submitted to a current injection, the maximum

ΣI

INJ(PIN) is the absolute sum of the

positive and negative injected currents (instantaneous values).

±25

Table 9.

Thermal characteristics

Symbol

Ratings

Value

Unit

TSTG

Storage temperature range

–65 to +150

°C

Maximum junction temperature

125

°C

Table 10.

General operating conditions(1)

Symbol

Parameter

Conditions

Min

Max

Unit

fHCLK

Internal AHB clock frequency

VOS bit in PWR_CR = 0

144

MHz

VOS bit in PWR_CR = 1

168

fPCLK1

Internal APB1 clock frequency

fPCLK2

Internal APB2 clock frequency

VDD

Standard operating voltage

1.8(2)

3.6

VDDA

(3)(4)

Analog operating voltage

(ADC limited to 1 M samples)

Must be the same potential as VDD

(5)

1.8(2)

3.6

Analog operating voltage

(ADC limited to 2 M samples)

2.4

3.6

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