STM32F407IE datasheet(59/154 Pages) STMICROELECTRONICS

59 / 154 page

STM32F405xx, STM32F407xx

Electrical characteristics

Doc ID 022152 Rev 1

59/154

VBAT

Backup operating voltage

1.65

3.6

VCAP1

When the internal regulator is ON,

VCAP_1 and VCAP_2 pins are used to

connect a stabilization capacitor.

When the internal regulator is OFF

(BYPASS_REG connected to VDD),

VCAP_1 and VCAP_2 must be supplied

from 1.2 V.

1.1

1.3

VCAP2

Power dissipation at TA = 85 °C for

suffix 6 or TA = 105 °C for suffix 7

(6)

LQFP64

TBD

LQFP100

TBD

LQFP144

TBD

LQFP176

TBD

UFBGA176

TBD

Ambient temperature for 6 suffix

version

Maximum power dissipation

–40

°C

Low power dissipation(7)

–40

105

Ambient temperature for 7 suffix

version

Maximum power dissipation

–40

105

°C

Low power dissipation(7)

–40

125

Junction temperature range

6 suffix version

–40

105

°C

7 suffix version

–40

125

TBD stands for “to be defined”.

If PDR_ON is set to VSS, this value can be lowered to 1.7 V when the device operates in a reduced temperature range (0 to

70 °C).

When the ADC is used, refer to Table 64: ADC characteristics.

If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V.

It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and

VDDA can be tolerated during power-up and power-down operation.

If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax.

In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax.

Table 10.

General operating conditions(1) (continued)

Symbol

Parameter

Conditions

Min

Max

Unit

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