STM32F407IE datasheet(64/154 Pages) STMICROELECTRONICS

64 / 154 page

Electrical characteristics

STM32F405xx, STM32F407xx

64/154

Doc ID 022152 Rev 1

from 90 to 120 MHz, 4 wait states from 120 to 150 MHz, and 5 wait states from 150 to

168 MHz,).

●

When the peripherals are enabled HCLK is the system clock, fPCLK1 = fHCLK/4, and

fPCLK2 = fHCLK/2, except is explicitly mentioned.

●

The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature

(TA), and the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.

Table 16.

Typical and maximum current consumption in Run mode, code with data processing

running from Flash memory (ART accelerator disabled)(1)

Symbol

Parameter

Conditions

fHCLK

Typ

Max(2)

Unit

TA = 25 °C TA = 85 °C TA = 105 °C

IDD

Supply current

in Run mode

External clock(3), all

peripherals enabled(4)

168 MHz

93.1

TBD

144 MHz

76.2

TBD

120 MHz

66.5

TBD

90 MHz

TBD

60 MHz

36.7

TBD

30 MHz

20.1

TBD

25 MHz

15.5

TBD

16 MHz(5)

TBD

8 MHz

6.4

TBD

4 MHz

TBD

2 MHz

2.8

TBD

External clock(4), all

peripherals disabled

168 MHz

46.4

TBD

144 MHz

40.3

TBD

120 MHz

36.6

TBD

90 MHz

TBD

60 MHz

21.5

TBD

30 MHz

12.2

TBD

25 MHz

9.7

TBD

16 MHz(5)

7.1

TBD

8 MHz

4.4

TBD

4 MHz

TBD

2 MHz

2.3

TBD

TBD stands for “to be defined”.

Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled.

External clock is 4 MHz and PLL is on when fHCLK > 25 MHz.

When the ADC is on (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for

the analog part.

In this case HCLK = system clock/2.

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