STM32F407IE datasheet(65/154 Pages) STMICROELECTRONICS

65 / 154 page

STM32F405xx, STM32F407xx

Electrical characteristics

Doc ID 022152 Rev 1

65/154

Table 17.

Typical and maximum current consumption in Run mode, code with data processing

running from Flash memory (ART accelerator enabled) or RAM (1)(2)

Symbol

Parameter

Conditions

fHCLK

Typ

Max(3)

Unit

TA =

25 °C

TA =

85 °C

TA =

105 °C

IDD

Supply current in

Run mode

External clock(4), all

peripherals enabled(5)

168 MHz

86.8

TBD

144 MHz

TBD

120 MHz

56.2

TBD

90 MHz

43.5

TBD

60 MHz

29.7

TBD

30 MHz

16.3

TBD

25 MHz

12.4

TBD

16 MHz(6)

8.7

TBD

8 MHz

5.1

TBD

4 MHz

3.3

TBD

2 MHz

2.4

TBD

External clock(4), all

peripherals disabled

168 MHz

39.8

TBD

144 MHz

30.8

TBD

120 MHz

TBD

90 MHz

20.4

TBD

60 MHz

14.3

TBD

30 MHz

8.2

TBD

25 MHz

6.4

TBD

16 MHz(6)

4.75

TBD

8 MHz

TBD

4 MHz

2.3

TBD

2 MHz

TBD

Code and data processing running from SRAM1 using boot pins.

TBD stands for “to be defined”.

Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled.

External clock is 4 MHz and PLL is on when fHCLK > 25 MHz.

When the ADC is on (ADON bit set in the ADC_CR2 register), add an additional power consumption of 1.6 mA per ADC for

the analog part.

In this case HCLK = system clock/2.

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