STM32F407IE datasheet(66/154 Pages) STMICROELECTRONICS

66 / 154 page

Electrical characteristics

STM32F405xx, STM32F407xx

66/154

Doc ID 022152 Rev 1

Table 18.

Typical and maximum current consumption in Sleep mode(1)

Symbol

Parameter

Conditions

fHCLK

Typ

Max(2)

Unit

TA = 25 °C TA = 85 °C

TA =

105 °C

IDD

Supply current in

Sleep mode

External clock(3),

all peripherals enabled(4)

168 MHz

TBD

144 MHz

TBD

120 MHz

TBD

90 MHz

TBD

60 MHz

TBD

30 MHz

TBD

25 MHz

TBD

16 MHz

TBD

8 MHz

3.6

TBD

4 MHz

2.4

TBD

2 MHz

1.9

TBD

External clock(3), all

peripherals disabled

168 MHz

TBD

144 MHz

TBD

120 MHz

TBD

90 MHz

TBD

60 MHz

TBD

30 MHz

3.5

TBD

25 MHz

2.5

TBD

16 MHz

2.1

TBD

8 MHz

1.7

TBD

4 MHz

1.5

TBD

2 MHz

1.4

TBD

TBD stands for “to be defined”.

Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled.

External clock is 4 MHz and PLL is on when fHCLK > 25 MHz.

Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only

while the ADC is on (ADON bit is set in the ADC_CR2 register).

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