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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STM32F407IE 데이터시트(PDF) 107 Page - STMicroelectronics |
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STM32F407IE 데이터시트(HTML) 107 Page - STMicroelectronics |
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107 / 154 page  STM32F405xx, STM32F407xx Electrical characteristics Doc ID 022152 Rev 1 107/154 CAN (controller area network) interface Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX). 5.3.20 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 64 are derived from tests performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 10. Table 63. Dynamics characteristics: Ethernet MAC signals for MII(1) 1. TBD stands for “to be defined”. Symbol Rating Min Typ Max Unit tsu(RXD) Receive data setup time TBD TBD TBD ns tih(RXD) Receive data hold time TBD TBD TBD ns tsu(DV) Data valid setup time TBD TBD TBD ns tih(DV) Data valid hold time TBD TBD TBD ns tsu(ER) Error setup time TBD TBD TBD ns tih(ER) Error hold time TBD TBD TBD ns td(TXEN) Transmit enable valid delay time 13.4 15.5 17.7 ns td(TXD) Transmit data valid delay time 12.9 16.1 19.4 ns Table 64. ADC characteristics(1) Symbol Parameter Conditions Min Typ Max Unit VDDA Power supply 1.8(2) -3.6 V VREF+ (3) Positive reference voltage 1.8(2)(4) -VDDA V fADC ADC clock frequency VDDA = 1.8 (2) to 2.4 V 0.6 - TBD MHz VDDA = 2.4 to 3.6 V 0.6 - TBD MHz fTRIG (5) External trigger frequency fADC = 36 MHz - - TBD kHz -- 17 1/fADC VAIN Conversion voltage range(6) 0 (VSSA or VREF- tied to ground) -VREF+ V RAIN (5) External input impedance See Equation 1 for details -- 50 k Ω RADC (5)(7) Sampling switch resistance 1.5 - 6 k Ω CADC (5) Internal sample and hold capacitor 4- TBD pF tlat (5) Injection trigger conversion latency fADC = 36 MHz - - 0.100 µs -- 3(8) 1/fADC tlatr (5) Regular trigger conversion latency fADC = 36 MHz - - 0.067 µs -- 2(8) 1/fADC |
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