STM32F407IE datasheet(132/154 Pages) STMICROELECTRONICS

132 / 154 page

Electrical characteristics

STM32F405xx, STM32F407xx

132/154

Doc ID 022152 Rev 1

NAND controller waveforms and timings

Figure 60 through Figure 63 represent synchronous waveforms and Table 79 provides the

corresponding timings. The results shown in this table are obtained with the following FSMC

configuration:

●

COM.FSMC_SetupTime = 0x01;

●

COM.FSMC_WaitSetupTime = 0x03;

●

COM.FSMC_HoldSetupTime = 0x02;

●

COM.FSMC_HiZSetupTime = 0x01;

●

ATT.FSMC_SetupTime = 0x01;

●

ATT.FSMC_WaitSetupTime = 0x03;

●

ATT.FSMC_HoldSetupTime = 0x02;

●

ATT.FSMC_HiZSetupTime = 0x01;

●

Bank = FSMC_Bank_NAND;

●

MemoryDataWidth = FSMC_MemoryDataWidth_16b;

●

ECC = FSMC_ECC_Enable;

●

ECCPageSize = FSMC_ECCPageSize_512Bytes;

●

TCLRSetupTime = 0;

●

TARSetupTime = 0;

tw(NIOWR)

FSMC_NIOWR low width

TBD

tv(NIOWR-D)

FSMC_NIOWR low to FSMC_D[15:0] valid

TBD

th(NIOWR-D)

FSMC_NIOWR high to FSMC_D[15:0] invalid

TBD

td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid

TBD

th(NCEx-NIOWR)

th(NCE4_1-NIOWR)

FSMC_NCEx high to FSMC_NIOWR invalid

FSMC_NCE4_1 high to FSMC_NIOWR invalid

TBD

td(NIORD-NCEx)

td(NIORD-NCE4_1)

FSMC_NCEx low to FSMC_NIORD valid FSMC_NCE4_1

low to FSMC_NIORD valid

-TBD

th(NCEx-NIORD)

th(NCE4_1-NIORD)

FSMC_NCEx high to FSMC_NIORD invalid

FSMC_NCE4_1 high to FSMC_NIORD invalid

TBD

tsu(D-NIORD)

FSMC_D[15:0] valid before FSMC_NIORD high

TBD

td(NIORD-D)

FSMC_D[15:0] valid after FSMC_NIORD high

TBD

tw(NIORD)

FSMC_NIORD low width

TBD

CL = 15 pF.

Based on characterization, not tested in production.

TBD stands for “to be defined”.

Table 78.

Switching characteristics for PC Card/CF read and write cycles(1)(2)(3) (continued)

Symbol

Parameter

Min

Max

Unit

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