PIC24F16KA102 datasheet(57/278 Pages) MICROCHIP

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 2008-2011 Microchip Technology Inc.

DS39927C-page 57

PIC24F16KA102 FAMILY

7.0

RESETS

The Reset module combines all Reset sources and

controls the device Master Reset Signal, SYSRST. The

following is a list of device Reset sources:

• POR: Power-on Reset

•MCLR: Pin Reset

•SWR: RESET Instruction

• WDTR: Watchdog Timer Reset

• BOR: Brown-out Reset

• Low-Power BOR/Deep Sleep BOR

• TRAPR: Trap Conflict Reset

• IOPUWR: Illegal Opcode Reset

• UWR: Uninitialized W Register Reset

Figure 7-1 displays a simplified block diagram of the

Reset module.

Any active source of Reset will make the SYSRST

signal active. Many registers associated with the CPU

and peripherals are forced to a known Reset state.

Most registers are unaffected by a Reset; their status is

unknown on a Power-on Reset (POR) and unchanged

by all other Resets.

All types of device Reset will set a corresponding status

bit in the RCON register to indicate the type of Reset

(see Register 7-1). A POR will clear all bits except for

the BOR and POR bits (RCON<1:0>) which are set.

The user may set or clear any bit at any time during

code execution. The RCON bits only serve as status

bits. Setting a particular Reset status bit in software will

not cause a device Reset to occur.

The RCON register also has other bits associated with

the Watchdog Timer (WDT) and device power-saving

states. The function of these bits is discussed in other

sections of this manual.

FIGURE 7-1:

RESET SYSTEM BLOCK DIAGRAM

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended

comprehensive

reference source. For more information

on Resets, refer to the “PIC24F Family

Reference Manual”

, Section 40. “Reset

with Programmable Brown-out Reset”

(DS39728).

Note:

Refer to the specific peripheral or CPU

section of this manual for register Reset

states.

Note:

The status bits in the RCON register

should be cleared after they are read so

that the next RCON register value, after a

device Reset, will be meaningful.

MCLR

VDD

VDD Rise

Detect

POR

Sleep or Idle

Brown-out

Reset

RESET

Instruction

WDT

Module

Glitch Filter

BOR

Trap Conflict

Illegal Opcode

Uninitialized W Register

SYSRST

BOREN<1:0>

RCON<SBOREN>

SLEEP

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