PIC24F16KA102 datasheet(67/278 Pages) MICROCHIP

67 / 278 page

 2008-2011 Microchip Technology Inc.

DS39927C-page 67

PIC24F16KA102 FAMILY

SR: ALU STATUS REGISTER

U-0

R-0, HSC

—

DC(1)

bit 15

bit 8

R/W-0, HSC R/W-0, HSC R/W-0, HSC

R-0, HSC

R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC

IPL2(2,3)

IPL1(2,3)

IPL0(2,3)

RA(1)

N(1)

OV(1)

Z(1)

C(1)

bit 7

bit 0

Legend:

HSC = Hardware Settable/Clearable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-9

Unimplemented:

Read as ‘0’

bit 7-5

IPL<2:0>:

CPU Interrupt Priority Level Status bits(2,3)

111

= CPU interrupt priority level is 7 (15); user interrupts disabled

110

= CPU interrupt priority level is 6 (14)

101

= CPU interrupt priority level is 5 (13)

100

= CPU interrupt priority level is 4 (12)

011

= CPU interrupt priority level is 3 (11)

010

= CPU interrupt priority level is 2 (10)

001

= CPU interrupt priority level is 1 (9)

000

= CPU interrupt priority level is 0 (8)

Note 1:

See Register 3-1 for the description of these bits, which are not dedicated to interrupt control functions.

The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt priority level.

The value in parentheses indicates the interrupt priority level if IPL3 = 1.

The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.

Note:

Bit 8 and Bits 4 through 0 are described in Section 3.0 “CPU”.

PIC24F16KA102 데이터시트(PDF) 67 Page - Microchip Technology

PIC24F16KA102 데이터시트(HTML) 67 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL