TNETX3100PGC datasheet(51/80 Pages) TI1

51 / 80 page

TNETX3100

ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS031D – JUNE 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

tertiary test access

The internal RAM access infers only that both DIO port and internal RAM structures are functioning correctly.

It does not provide information on the TNETX3100 data paths (to and from the RAMS) during normal frame

operations or an indication of the control-path functionality. To assist with this further, the proposed tests are

as follows:

• DRAM access — this test proves that the data path between FIFO and DRAM is functioning, along with

certain sections of the queue manager and FIFO logic operations.

• Frame forwarding — frame data is forwarded from one port to the next using a loopback mode. This

builds on the previous tests, and ensures that the data path to and from the protocol handlers and

control paths are operational. The number of ports that take part in forwarding is controlled using the

VLAN registers, allowing any number of ports to be tested in this mode. Single connections can be

tested, allowing individual protocol-handler data paths-to-FIFO connections to be tested or

multiple-port testing that allows reduced system test time.

external DRAM test access

Using the incremental test approach (after the FIFO is tested and verified), the data path to and control of the

external DRAM is verified.

DRAM writes are carried out by first constructing a buffer in the FIFO (64 bytes), and then initiating a buffer write

from the FIFO to the DRAM. The buffer is transferred like a normal buffer transfer in a 17-write DRAM burst.

The forward-pointer field is mapped to the DRAM data register, and the flag data fields are mapped to the DRAM

flag register.

Reading from the DRAM performs a buffer transfer to the FIFO from which individual bytes can be read (and

tested) through the DIO interface. The flag bytes and forward-pointer bytes are transferred from the DRAM to

the DRAM data and DRAM flag registers for reading.

The buffer transfer mechanism, when operated in DRAM test-access mode, does not check the flag status. No

actions are performed, depending on the status of the flags. The transfer is a test data transfer, with no attempt

made to comprehend flag contents.

After completion of the DRAM testing, the TNETX3100 should be reset before normal switching activity is

resumed. This ensures that the TNETX3100 is returned to a defined state before normal functionality is

resumed. This mechanism is intended primarily for DRAM testing and is not a part of a breakpoint/debug

mechanism.

For more information refer, to the

DRAM test-access operation register section in the TNETX3100 register

descriptions.

TNETX3100PGC 데이터시트(PDF) 51 Page - Texas Instruments