TNETX3100PGC datasheet(7/80 Pages) TI1

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TNETX3100

ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS031D – JUNE 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions (Continued)

10-/100-Mbit/s MAC interface (ports 00–01)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

M00COL

162

Collision sense High

network collision and low

no network collision

M01COL

184

Collision sense. High = network collision and low = no network collision.

M00CRS

164

Carrier sense High

frame carrier signal is received and low

no frame carrier signal is received

M01CRS

185

Carrier sense. High = frame carrier signal is received and low = no frame carrier signal is received.

M00DUPLEX

173

I/O

Duplex selector. MXXDUPLEX switches the interface between full- and half-duplex operation

(low

half duplex high

full duplex) The M00DUPLEX and M01DUPLEX inputs have active

M01DUPLEX

194

I/O

(low = half duplex, high = full duplex). The M00DUPLEX and M01DUPLEX inputs have active

pulldown circuits used to force the inputs low when FORCEHD bit is set.

M00LINK

176

Link selector MXXLINK indicates the condition of the port connection ( low

no link high

link)

M01LINK

197

Link selector. MXXLINK indicates the condition of the port connection ( low = no link, high = link).

M00RCLK

166

Receive clock MXXRCLK source is from the external PHY

M01RCLK

187

Receive clock. MXXRCLK source is from the external PHY.

M00RXDV

171

Receive data valid MXXRXDV indicates data on MXXRXD3 MXXRXD0 is valid

M01RXDV

192

Receive data valid. MXXRXDV indicates data on MXXRXD3–MXXRXD0 is valid.

M00RXER

172

Receive error MXXRXER indicates reception of a coding error on received data

M01RXER

193

Receive error. MXXRXER indicates reception of a coding error on received data.

M00RXD0

167

M01RXD0

188

M00RXD1

168

M01RXD1

189

Receive data. Nibble receive data MXXRXD3–MXXRXD0 is from the physical media-dependent

front end Data is synchronous to MXXRCLK If MWIDTH bit in the port control register and

M00RXD2

169

front end. Data is synchronous to MXXRCLK. If MWIDTH bit in the port control register and

M00SPEED terminal are set low, then data is received on M00RXD0 and M01RXD0 terminals.

M01RXD2

190

M00SPEED terminal are set low, then data is received on M00RXD0 and M01RXD0 terminals.

M00RXD3

170

M01RXD3

191

M00SPEED

175

Bit-rate selection speed. The speed of the MAC interface is determined by the logic level on

M01SPEED

196

MXXSPEED (low = 10 Mbit/s, high = 100 Mbit/s).

M00TCLK

155

Transmit clock Transmit clock source is from the external PHY

M01TCLK

177

Transmit clock. Transmit clock source is from the external PHY.

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