TNETX3100PGC datasheet(72/80 Pages) TI1

72 / 80 page

TNETX3100

ThunderSWITCH™ 10-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS031D – JUNE 1997 – REVISED OCTOBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

operating characteristics over recommended operating conditions (see Figure 23)

EEPROM interface

NO.

PARAMETER

MIN

MAX

UNIT

fclock (ECLK)

Clock frequency, ECLK

kHz

td (ECLKH–EDIOL)

Delay time, from ECLK

↑ to EDIO↓ (see Note 14)

µs

td (EDIOL–ECLKL)

Delay time, from EDIO

↓ to ECLK↓ (see Note 14)

µs

td (ECLKL–EDIOX)

Delay time, from ECLK

↓ to EDIO changing (see Note 15)

µs

td (EDIOV–ECLKH)

Delay time, from EDIO valid output to ECLK

↑

µs

td (ECLKL–EDIOV)

Delay time, from ECLK

↓ to EDIO valid

µs

td (ECLKL–EDIOX)

Delay time, from ECLK

↓ to EDIO changing (see Note 16)

µs

td (ECLKH–EDIOX)

Delay time, from ECLK

↑ to EDIO invalid

µs

td (EDIOV–ECLKH)

Delay time, from EDIO valid input to ECLK

↑

µs

NOTES: 14. This is a start-condition delay time during ECLK high.

15. This is a changing-data condition delay time for output EDIO.

16. This is a changing-data condition delay time for input EDIO.

ECLK

(output)

EDIO

(output)

EDIO

(input)

VALID

Figure 23. EEPROM Interface Timing

TNETX3100PGC 데이터시트(PDF) 72 Page - Texas Instruments

TNETX3100PGC 데이터시트(HTML) 72 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

데이터시트 다운로드

링크 URL