CXD3003 datasheet(103/137 Pages) SONY

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CXD3003R

§5-9. MIRR and DFCT Signal Generation

The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz (when MCK = 128Fs) and

loaded. The MIRR and DFCT signals are generated from this RF signal.

MIRR Signal Generation

The loaded RF signal is applied to peak hold and bottom hold circuits.

An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is

generated from the average of this envelope waveform.

The MIRR signal is generated by comparing the waveform generated by subtracting the bottom hold value

from the peak hold value with this MIRR comparator level. (See Fig. 5-11.)

The bottom hold speed and mirror sensitivity can be selected from 4 values using D7 and 6, and D5 and 4,

respectively, of $3C.

Peak Hold

Bottom Hold

Peak Hold

– Bottom Hold

MIRR

MIRR Comp

(Mirror comparator level)

Peak Hold1

Peak Hold2

– Peak Hold1

DFCT

(Defect comparator level)

SDF

Fig. 5-11.

DFCT Signal Generation

The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is

generated by comparing the difference between these two peak hold waveforms with the DFCT comparator

level. (See Fig. 5-12.)

The DFCT comparator level can be selected from four values using D13 and D12 of $3B.

Fig. 5-12.

CXD3003 데이터시트(PDF) 103 Page - Sony Corporation