WM8912 datasheet(46/128 Pages) WOLFSON

46 / 128 page

WM8912

Production Data

PD, Rev 4.0, September 2010

REFERENCE VOLTAGES AND MASTER BIAS

This section describes the analogue reference voltage and bias current controls. Note that, under the

recommended usage conditions of the WM8912, these features will be configured by scheduling the

default Start-Up and Shutdown sequences as described in the “Control Write Sequencer” section. In

these cases, the user does not need to set these register fields directly.

The analogue circuits in the WM8912 require a mid-rail analogue reference voltage, VMID. This

reference is generated from AVDD via a programmable resistor chain.

VMID is enabled by setting the VMID_ENA register bit. The programmable resistor chain is

configured by VMID_RES [1:0], and can be used to optimise the reference for normal operation, low

power standby or for fast start-up as described in Table 29. For normal operation, the VMID_RES

field should be set to 01.

The analogue circuits in the WM8912 require a bias current. The normal bias current is enabled by

setting BIAS_ENA. Note that the normal bias current source requires VMID to be enabled also.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R5 (05h)

VMID

Control (0)

2:1

VMID_RES

[1:0]

VMID Divider Enable and Select

00 = VMID disabled (for OFF mode)

01 = 2 x 50k divider (for normal operation)

10 = 2 x 250k divider (for low power standby)

11 = 2 x 5k divider (for fast start-up)

VMID_ENA

Enable VMID master bias current source

0 = Disabled

1 = Enabled

R4 (04h)

Bias Control

(0)

BIAS_ENA

Enables the Normal bias current generator

(for all analogue functions)

0 = Disabled

1 = Enabled

Table 29 Reference Voltages and Master Bias Enable

CHARGE PUMP

The WM8912 incorporates a dual-mode Charge Pump which generates the supply rails for the

headphone and line output drivers, HPOUTL, HPOUTR, and LINEOUTL and LINEOUTR. The

Charge Pump has a single supply input, CPVDD, and generates split rails CPVOUTP and

CPVOUTN according to the selected mode of operation. The Charge Pump connections are

illustrated in Figure 24 (see the “Electrical Characteristics” section for external component values).

An input decoupling capacitor may also be required at CPVDD, depending upon the system

configuration.

Figure 24 Charge Pump External Connections

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