WM8912 datasheet(53/128 Pages) WOLFSON

53 / 128 page

Production Data

WM8912

PD, Rev 4.0, September 2010

DC SERVO READBACK

The current DC offset value for each Line and Headphone output channel can be read in two’s

complement format from the DCS_DAC_WR_VAL_n [7:0] bit fields in Registers R73, R74, R75 and

R76. Note that these values may form the basis of settings that are subsequently used by the DC

Servo in DAC Write mode.

DIGITAL AUDIO INTERFACE

The digital audio interface is used for inputting DAC data to the WM8912. The digital audio interface

uses three pins:

•

DACDAT: DAC data input

•

LRCLK: Left/Right data alignment clock

•

BCLK: Bit clock, for synchronisation

The clock signals BCLK and LRCLK can be outputs when the WM8912 operates as a master, or

inputs when it is a slave (see “Master and Slave Mode Operation”, below).

Four different audio data formats are supported:

•

Left justified

•

Right justified

•

I2S

•

DSP mode

All four of these modes are MSB first. They are described in “Audio Data Formats (Normal Mode)”,

below. Refer to the “Signal Timing Requirements” section for timing information.

Time Division Multiplexing (TDM) is available in all four data format modes. The WM8912 can be

programmed to receive data in one of two time slots.

PCM operation is supported using the DSP mode.

MASTER AND SLAVE MODE OPERATION

The WM8912 digital audio interface can operate in master or slave mode, as shown in Figure 25 and

Figure 26.

Figure 25 Master Mode

Figure 26 Slave Mode

In master mode, BCLK is derived from SYSCLK via a programmable division set by BCLK_DIV.

In master mode, LRCLK is derived from BCLK via a programmable division set by LRCLK_RATE.

The BCLK input to this divider may be internal or external, allowing mixed master and slave modes.

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