WM8912 datasheet(100/128 Pages) WOLFSON

100 / 128 page

WM8912

Production Data

PD, Rev 4.0, September 2010

100

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R25 (19h)

Audio

Interface 1

AIFDAC_TDM

DAC TDM Enable

0 = Normal DACDAT operation

1 = TDM enabled on DACDAT

AIFDAC_TDM_

CHAN

DACDAT TDM Channel Select

0 = DACDAT data input on slot 0

1 = DACDAT data input on slot 1

AIF_TRIS

Audio Interface Tristate

0 = Audio interface pins operate normally

1 = Tristate all audio interface pins

AIF_BCLK_INV

BCLK Invert

0 = BCLK not inverted

1 = BCLK inverted

BCLK_DIR

Audio Interface BCLK Direction

0 = BCLK is input

1 = BCLK is output

AIF_LRCLK_IN

LRC Polarity / DSP Mode A-B select.

Right, left and I2S modes – LRC polarity

0 = Not Inverted

1 = Inverted

DSP Mode – Mode A-B select

0 = MSB is available on 2nd BCLK rising edge after

LRC rising edge (mode A)

1 = MSB is available on 1st BCLK rising edge after

LRC rising edge (mode B)

3:2

AIF_WL [1:0]

Digital Audio Interface Word Length

00 = 16 bits

01 = 20 bits

10 = 24 bits

11 = 32 bits

1:0

AIF_FMT [1:0]

Digital Audio Interface Format

00 = Right Justified

01 = Left Justified

10 = I2S

11 = DSP

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

R26 (1Ah)

Audio

Interface 2

11:8

OPCLK_DIV

[3:0]

0000

GPIO Output Clock Divider

0000 = SYSCLK

0001 = SYSCLK / 2

0010 = SYSCLK / 3

0011 = SYSCLK / 4

0100 = SYSCLK / 5.5

0101 = SYSCLK / 6

0110 = SYSCLK / 8

0111 = SYSCLK / 12

1000 = SYSCLK / 16

1001 to 1111 = Reserved

WM8912 데이터시트(PDF) 100 Page - Wolfson Microelectronics plc

WM8912 데이터시트(HTML) 100 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL