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WM8961GEFL/V 데이터시트(PDF) 48 Page - Wolfson Microelectronics plc |
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WM8961GEFL/V 데이터시트(HTML) 48 Page - Wolfson Microelectronics plc |
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48 / 116 page ![]() WM8961 Pre-Production w PP, August 2009, Rev 3.1 48 SPEAKER OUTPUT PGA VOLUME CONTROL The signal volume on SPK_L and SPK_R can be independently adjusted under software control by writing to SPKLVOL and SPKRVOL, as shown in Figure 21. Figure 21 Speaker Volume PGA A zero cross detect on the analogue output may also be enabled when changing the gain setting to minimize audible clicks and zipper noise as the gain updates. If zero cross is enabled a timeout is also available to update the gain if a zero cross does not occur. This function may be enabled by setting TOEN in register R23 (17h). The timeout period is set by CLK_TO_DIV[1:0]. The volume control PGAs are enabled using SPKL_PGA and SPKR_PGA. |
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