WM8961GEFLSLASHV datasheet(63/116 Pages) WOLFSON

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WM8961

Pre-Production

PP, August 2009, Rev 3.1

AUDIO INTERFACE OUTPUT TRISTATE

BCLK to inputs. In Slave mode (MS=0) LRC and BCLK are by default configured as inputs and only

ADCDAT will be tri-stated, (see Table 45).

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R24 (18h)

Additional

Control (2)

TRIS

Tri-states ADCDAT and switches LRC and

BCLK to inputs.

0 = ADCDAT is an output; LRC and BCLK are

inputs (slave mode) or outputs (master mode)

1 = ADCDAT is tri-stated; LRC and BCLK are

inputs

Table 45 Tri-stating the Audio Interface

COMPANDING

The WM8961 supports A-law and

μ-law companding on both transmit (ADC) and receive (DAC) sides.

Companding can be enabled on the DAC or ADC audio interfaces by writing the appropriate value to

the DACCOMP or ADCCOMP register bits respectively.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R9 (09h)

Audio

Interface (2)

2:1

ADCCOMP

ADC companding

00 = off

01 = reserved

10 = μ-law

11 = A-law

4:3

DACCOMP

DAC companding

00 = off

01 = reserved

10 = μ-law

11 = A-law

Table 46 Companding Control

Companding involves using a piecewise linear approximation of the following equations (as set out by

ITU-T G.711 standard) for data compression:

μ-law (where μ=255 for the U.S. and Japan):

F(x) = ln( 1 +

μ|x|) / ln( 1 + μ)

-1 ≤ x ≤ 1

law (where A=87.6 for Europe):

F(x) = A|x| / ( 1 + lnA)

} for x ≤ 1/A

F(x) = ( 1 + lnA|x|) / (1 + lnA)

} for 1/A ≤ x ≤ 1

The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted

for

μ-law, all even data bits are inverted for A-law). The data will be transmitted as the first 8 MSB’s of

data.

Companding converts 13 bits (

μ-law) or 12 bits (A-law) to 8 bits using non-linear quantization. The

input data range is separated into 8 levels, allowing low amplitude signals better precision than that of

high amplitude signals. This is to exploit the operation of the human auditory system, where louder

sounds do not require as much resolution as quieter sounds. The companded signal is an 8-bit word

containing sign (1-bit), exponent (3-bits) and mantissa (4-bits).

8-bit mode is automatically selected during companding. That is whenever DACCOMP[2]=1 or

ADCCOMP[2]=1. The use of 8-bit data allows samples to be passed using as few as 8 BCLK cycles

per LRC frame. When using DSP mode B, 8-bit data words may be transferred consecutively every 8

BCLK cycles.

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